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LTC2152-14/ LTC2151-14/LTC2150-14
Electrical Specifications Subject to Change
14-Bit 250Msps/ 210Msps/170Msps ADCs FEATURES
n n n n n n n n n n n n
DESCRIPTION
The LTC(R)2152-14/LTC2151-14/LTC2150-14 are 250Msps/ 210Msps/170Msps 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 70dB SNR and 90dB spurious free dynamic range (SFDR). The latency is only five clock cycles. DC specs include 0.85LSB INL (typ), 0.25LSB DNL (typ) and no missing codes over temperature. The transition noise is 1.82LSBRMS. The digital outputs are Double-Data Rate (DDR) LVDS. The ENC+ and ENC- inputs can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
70dB SNR 90dB SFDR Low Power: 338mW/316mW/290mW Total Single 1.8V Supply DDR LVDS Outputs Easy-to-Drive 1.5VP-P Input Range 1.25GHz Full Power Bandwidth S/H Optional Clock Duty Cycle Stabilizer Low Power Sleep and Nap Modes Serial SPI Port for Configuration Pin Compatible with 12-Bit Versions 40-Pin (6mm x 6mm) QFN Package
APPLICATIONS
n n n n n n
Communications Cellular Basestations Software Defined Radios Medical Imaging High Definition Video Testing and Measurement Instruments
TYPICAL APPLICATION
VDD OVDD D12_13 * * * D0_1
32K Point FFT, fIN = 15MHz, -1dBFS, 250Msps
0 -20 AMPLITUDE (dBFS)
ANALOG INPUT
S/H
14-BIT PIPELINED ADC
CORRECTION LOGIC
OUTPUT DRIVERS
DDR LVDS
-40 -60 -80
CLOCK
CLOCK/DUTY CYCLE CONTROL
21521014 TA01a
OGND
-100 -120
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0
20
40 60 80 100 FREQUENCY (MHz)
120
21521014 TA01b
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LTC2152-14/ LTC2151-14/LTC2150-14 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW PAR/SER D12_13+ D12_13- D10_11+ D2_3+ D10_11- 30 OVDD 29 D8_9+ 28 D8_9- 27 CLKOUT+ GND 41 26 CLKOUT - 25 D6_7+ 24 D6_7- 23 D4_5+ 22 D4_5- 21 OGND 11 12 13 14 15 16 17 18 19 20 GND D0_1- D0_1+ D2_3- OVDD ENC+ ENC- OF - OF +
Supply Voltage VDD, OVDD................................................ -0.3V to 2V Analog Input Voltage AINA/B+, AINA/B -, PAR/SER, SENSE (Note 3)........................ -0.3V to (VDD + 0.2V) Digital Input Voltage ENC+, ENC- (Note 3) ................ -0.3V to (VDD + 3.9V) CS, SDI, SCK (Note 4).............. -0.3V to (VDD + 0.3V) SDO (Note 4)............................................. -0.3V to 3.9V Digital Output Voltage ................ -0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2152C, LTC2151C, LTC2150C ............. 0C to 70C LTC2152I, LTC2151I, LTC2150I ............-40C to 85C Storage Temperature Range .................. -65C to 150C
40 39 38 37 36 35 34 33 32 31 VDD 1 VDD 2 GND 3 AIN+ 4 AIN- 5 GND 6 SENSE 7 VREF 8 VCM 9 GND 10
UJ PACKAGE 40-LEAD (6mm x 6mm) PLASTIC QFN TJMAX = 150C, JA = 33C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC2152CUP-14#PBF LTC2152IUP-14#PBF LTC2151CUP-14#PBF LTC2151IUP-14#PBF LTC2150CUP-14#PBF LTC2150IUP-14#PBF TAPE AND REEL LTC2152CUP-14#TRPBF LTC2152IUP-14#TRPBF LTC2151CUP-14#TRPBF LTC2151IUP-14#TRPBF LTC2150CUP-14#TRPBF LTC2150IUP-14#TRPBF PART MARKING* LTC2152-14 LTC2152-14 LTC2151-14 LTC2151-14 LTC2150-14 LTC2150-14 PACKAGE DESCRIPTION 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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GND
SDO
SCK
SDI
CS
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LTC2152-14/ LTC2151-14/LTC2150-14 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS
l
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise
MIN 14 -3.7 -1 -15
LTC2152-14 TYP MAX 0.85 0.5 5 1 20 30 10 1.85 3.7 1 15
MIN 14 -3.8 -1 -15
LTC2151-14 TYP MAX 1 0.5 5 1 20 30 10 1.8 3.8 1 15
LTC2150-14 MIN TYP MAX 14 -3.8 -1 -15 1 0.5 3 1 20 30 10 1.8 3.8 1 15
UNITS Bits LSB LSB mV %FS V/C ppm/C ppm/C LSBRMS
Differential Analog Input (Note 6) l Differential Analog Input (Note 7) External Reference Internal Reference External Reference External Reference
l l l
ANALOG INPUT
SYMBOL PARAMETER VIN VIN(CM) VSENSE IIN1 IIN2 IIN3 tAP tJITTER CMRR BW-3B
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS 1.7V < VDD < 1.9V Differential Analog Input (Note 8) External Reference Mode 0 < AIN+, AIN- < VDD 1.2V < SENSE < 1.3V 0 < PAR/SER < VDD
l l l l l l
MIN VCM - 20mV 1.200 -1 -1 -1
TYP 1.5 VCM 1.250
MAX VCM + 20mV 1.300 1 1 1
UNITS VP-P V V A A A ns psRMS dB MHz
Analog Input Range (AIN+ - AIN-) Analog Input Common Mode (AIN+ + AIN-)/2 External Reference Mode Analog Input Leakage Current SENSE Input Leakage Current PAR/SER Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full-Power Bandwidth
1 0.15 75 1250
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 5)
SYMBOL SNR PARAMETER Signal-to-Noise Ratio CONDITIONS 5MHz Input 70MHz Input 140MHz Input MIN LTC2152-14 TYP MAX 70 69.7 69 90 85 80 95 95 85 69.9 69.4 68.8 MIN LTC2151-14 TYP MAX 70 69.7 69 90 85 80 95 95 85 69.9 69.4 68.8 LTC2150-14 MIN TYP MAX 70 69.7 69 90 85 80 98 95 85 69.9 69.4 68.8 UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
DYNAMIC ACCURACY
l
TBD
TBD
TBD TBD
SFDR
Spurious Free Dynamic Range 5MHz Input 2nd or 3rd Harmonic 70MHz Input 140MHz Input
l
TBD
TBD
Spurious Free Dynamic Range 5MHz Input 4th Harmonic 70MHz Input www..com or Higher 140MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 70MHz Input 140MHz Input
l
TBD
TBD
TBD
l
TBD
TBD
TBD
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LTC2152-14/ LTC2151-14/LTC2150-14 INTERNAL REFERENCE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Temperature Drift VCM Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation -400A < IOUT < 1mA 1.7V < VDD < 1.9V -1mA < IOUT < 1mA IOUT = 0 1.225 CONDITIONS IOUT = 0
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN 0.444 * VDD - 15mV TYP 0.444 * VDD 37 4 1.250 30 7 0.6 1.275 MAX 0.444 * VDD + 15mV UNITS V ppm/C V ppm/C mV/V
POWER REQUIREMENTS
SYMBOL PARAMETER VDD OVDD IVDD IOVDD PDISS PSLEEP PNAP Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current Power Dissipation Nap Mode Power Sleep Mode Power CONDITIONS (Note 9)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN
l l l
LTC2152-14 TYP MAX 1.8 1.8 160 28 47 338 372 113.5 <2 1.9 1.9
MIN 1.7 1.7
LTC2151-14 TYP MAX 1.8 1.8 149 27 45 316 249 106.2 <2 1.9 1.9
LTC2150-14 MIN TYP MAX 1.7 1.7 1.8 1.8 135 26 44 290 322 97.2 <2 1.9 1.9
UNITS V V mA mA mA mW mW mW mW
1.7 1.7
LVDS Mode (Note 9) 1.75mA LVDS Mode 3.5mA LVDS Mode 1.75mA LVDS Mode 3.5mA LVDS Mode Clocked at fS(MAX) Clocked at fS(MAX)
l l
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC- ) VID VICM VIN RIN CIN VIH Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage (Note 8)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS
l l l
MIN 0.2 1.1 0.2
TYP 1 1.2
MAX 1.9 1.5 1.9
UNITS V V V V k pF V
Internally Set Externally Set (Note 8) ENC+, ENC- to GND (See Figure 2) (Note 8) VDD = 1.8V VDD = 1.8V VIN = 0V to 1.8V (Note 8) VDD = 1.8V, SDO = 0V SDO = 0V to 3.6V (Note 8)
10 2
l l l
DIGITAL INPUTS (CS, SDI, SCK) 1.3 0.6 -10 3 200
l
VIL Low Level Input Voltage www..com IIN Input Current CIN ROL IOH COUT Input Capacitance Logic Low Output Resistance to GND Logic High Output Leakage Current Output Capacitance
V A pF
10
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used) -10 4 10 A pF
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LTC2152-14/ LTC2151-14/LTC2150-14 DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER DIGITAL DATA OUTPUTS VOD VOS RTERM Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V
l l l l
MIN 247 125 1.125 1.125
TYP 350 175 1.250 1.250 100
MAX 454 250 1.375 1.375
UNITS mV mV V V
TIMING CHARACTERISTICS
SYMBOL fS tL tH PARAMETER Sampling Frequency ENC Low Time (Note 8) ENC High Time (Note 8)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On MIN 10 1.9 1.9 1.9 1.9 LTC2152-14 TYP MAX 250 2 50 2 50 2 50 2 50 MIN 10 2.26 1.5 2.26 1.5 LTC2151-14 TYP MAX 210 2.38 50 2.38 50 2.38 50 2.38 50 LTC2150-14 MIN TYP MAX 10 170 2.79 2.94 50 1.5 2.94 50 2.79 2.94 50 1.5 2.94 50 UNITS MHz ns ns ns ns
l l l l l
DIGITAL DATA OUTPUTS LTC215X-14 SYMBOL tD tC tSKEW PARAMETER ENC to Data Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Pipeline Latency SPI Port Timing (Note 8) tSCK tS tH tDS tDH tDO SCK Period CS to SCK Set-Up Time SCK to CS Hold Time SDI Set-Up Time SDI Hold Time SCK Falling to SDO Valid Readback Mode RPULLUP = 2k, CSDO = 20pF Write Mode, CSDO = 20pF Readback Mode RPULLUP = 2k, CSDO = 20pF
l l l l l
CONDITIONS CL = 5pF CL = 5pF tD - tC
MIN
l l l
TYP 2 1.6 0.4
MAX 2.3 2 0.55 5
UNITS ns ns ns Cycles ns ns ns ns ns ns
1.7 1.3 0.3 5 40 250 5 5 5 5
125
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin www..com voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 250MHz (LTC2152), 210MHz (LTC2151), or 170MHz (LTC2150), LVDS outputs, differential ENC+/ENC- = 2VP-P sine wave, input range = 1.5VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from -0.5LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2's complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions.
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LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2152-14: Integral Nonlinearity (INL)
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 4096 8192 12288 OUTPUT CODE 16384
21521014 G01
LTC2152-14: Differential Nonlinearity (DNL)
0 0.4 -20 AMPLITUDE (dBFS) DNL ERROR (LSB) 0.2 -40 -60 -80
LTC2152-14: 32K Point FFT, fIN = 15MHz, -1dBFS, 250Msps
INL ERROR (LSB)
0
-0.2
-100 -0.4 0 4096 8192 12288 OUTPUT CODE 16384
21521014 G02
-120
0
20
40 60 80 100 FREQUENCY (MHz)
120
21521014 G03
LTC2152-14: 32K Point FFT, fIN = 70MHz, -1dBFS, 250Msps
0 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -60 -80 0 -20 -40 -60 -80
LTC2152-14: 32K Point FFT, fIN = 122MHz, -1dBFS, 250Msps
0 -20 AMPLITUDE (dBFS) 0 20 40 60 80 100 FREQUENCY (MHz) 120 -40 -60 -80
LTC2152-14: 32K Point FFT, fIN = 171MHz, -1dBFS, 250Msps
-100 -120
-100 -120
-100 -120
0
20
40 60 80 100 FREQUENCY (MHz)
120
0
20
40 60 80 100 FREQUENCY (MHz)
120
21521014 G04
21521014 G05
21521014 G06
LTC2152-14: 32K Point FFT, fIN = 229MHz, -1dBFS, 250Msps
0 -20 AMPLITUDE (dBFS) -40 -60 -80 AMPLITUDE (dBFS) 0 40 60 80 100 FREQUENCY (MHz) 0 -20 -40 -60 -80
LTC2152-14: 32K Point FFT, fIN = 381MHz, -1dBFS, 250Msps
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-100 -120
-100 -120
20
120
0
20
21521014 G07
40 60 80 100 FREQUENCY (MHz)
120
21521014 G08
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LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2152-14: 32K Point FFT, fIN = 421MHz, -1dBFS, 250MHz
0 -20
AMPLITUDE (dBFS) 0 -20 -40 -60 -80
LTC2152-14: 32K Point FFT, fIN = 571MHz, -1dBFS, 250MHz
0 -20 AMPLITUDE (dBFS)
0 20 100 120 40 60 80 INPUT FREQUENCY (MHz) 21521014 G10
LTC2152-14: 32K Point FFT, fIN = 907MHz, -1dBFS, 250Msps
AMPLITUDE (dBFS)
-40 -60 -80
-40 -60 -80
-100 -120
-100 -120
-100 -120
0
20
40 60 80 100 120 INPUT FREQUENCY (MHz) 21521014 G09
0
20
40 60 80 100 120 INPUT FREQUENCY (MHz) 21521014 G11
LTC2152-14: 32K Point 2-Tone FFT, fIN = 70.5MHz and 69.5MHz, 250Msps
0 -20 AMPLITUDE (dBFS) -40 COUNT -60 -80 4000 3500 3000
LTC2152-14: Shorted Input Histogram
50 45 40 IOVDD (mA) 35 30 25 20 8200 8208 8204 OUTPUT CODE 8212 8216
215210 G13
LTC2152-14: IOVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS
LVDS CURRENT 3.5mA
2500 2000 1500 1000
LVDS CURRENT 1.75mA
-100 -120
500 0 20 40 60 80 100 120 INPUT FREQUENCY (MHz) 21521014 G12 0 8196
15
0
50
100 150 200 SAMPLE RATE (Msps)
250
21521014 G14
LTC2152-14: IVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS
170 160 150 IVDD (mA) 140 130 120 110 120 100 SFDR (dBFS) 80
LTC2152-14: SFDR vs Input Level, fIN = 70MHz, 1.5V Range, 250Msps
dBFS
dBc 60 40 20 0 -80 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE (dBFS)
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0
50
100 150 200 SAMPLE RATE (Msps)
250
0
21521014 G15
21521014 G16
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LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2152-14: SNR vs Input Level, fIN = 70MHz, 1.5V Range, 250Msps
70 60 50 SNR (dBFS) 40 30 20 10 0 -60 -50 -40 -30 -20 AMPLITUDE (dBFS) -10
21521014 G17
LTC2152-14: SFDR vs Input Frequency, -1dBFS, 1.5V Range, 250Msps
90 80 70 INPUT LEVEL (dBc) SFDR (dBFS) 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz)
21521014 G18
20 10 0 -10
dBFS
dBc
-20 -30 -40 -50 -60 -70 0
LTC2152-14: SNR vs Input Frequency, -1dBFS, 1.5V Range, 250Msps
75 70 FS AMPLITUDE (-1dB) 65 SNR (dBFS) 60 55 50 45 40 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz)
21521014 G19
LTC2152-14: Frequency Response
-0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 100 1000 INPUT FREQUENCY (MHz)
21521014 G20
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LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2151-14: Integral Nonlinearity INL
2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 4096 8192 12288 OUTPUT CODE 16384
21521014 G21
LTC2151-14: Differential Nonlinearity DNL
0 0.4 -20 AMPLITUDE (dBFS) 0 4096 8192 12288 OUTPUT CODE 16384
21521014 G22
LTC2151-14: 32K Point FFT, fIN = 15MHz, -1dBFS, 210Msps
0.2
-40 -60 -80
0
-0.2
-100 -0.4 -120 0 20 40 60 80 FREQUENCY (MHz) 100
21521014 G23
0 -20 AMPLITUDE (dBFS)
LTC2151-14: 32K Point FFT, fIN = 71MHz, -1dBFS, 210Msps
0 -20 AMPLITUDE (dBFS) -40 -60 -80
LTC2151-14: 32K Point FFT, fIN = 101MHz, -1dBFS, 210Msps
0 -20 AMPLITUDE (dBFS) 0 20 40 60 80 FREQUENCY (MHz) 100
21521014 G25
LTC2151-14: 32K Point FFT, fIN = 171MHz, -1dBFS, 210Msps
-40 -60 -80
-40 -60 -80
-100 -120
-100 -120
-100 -120
0
20
40 60 80 FREQUENCY (MHz)
100
21521014 G24
0
20
40 60 80 FREQUENCY (MHz)
100
21521014 G26
LTC2151-14: 32K Point FFT, fIN = 227MHz, -1dBFS, 210Msps
0 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -60 -80
0 -20 -40 -60 -80
LTC2151-14: 32K Point FFT, fIN = 379MHz, -1dBFS, 210Msps
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-100 -120
-100 -120
0
20
40 60 80 FREQUENCY (MHz)
100
21521014 G27
0
20
40 60 80 FREQUENCY (MHz)
100
21521014 G28
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LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL PERFORMANCE CHARACTERISTICS
0 -20 AMPLITUDE (dBFS) -40 -60 -80 AMPLITUDE (dBFS)
LTC2151-14: 32K Point FFT, fIN = 417MHz, -1dBFS, 210Msps
0 -20
LTC2151-14: 32K Point FFT, fIN = 571MHz, -1dBFS, 210Msps
0 -20 AMPLITUDE (dBFS) -40 -60 -80
LTC2151-14: 32K Point FFT, fIN = 907MHz, -1dBFS, 210Msps
-40 -60 -80
-100 -120
-100 -120
-100 -120
0
20
40 60 80 FREQUENCY (MHz)
100
21521014 G29
0
20
40 60 80 FREQUENCY (MHz)
100
21521014 G30
0
20
40 60 80 FREQUENCY (MHz)
100
21521014 G31
LTC2151-14: 32K Point 2-Tone FFT, fIN = 70.5 and 69.5MHz, 210Msps
0 -20 AMPLITUDE (dBFS) -40 COUNT -60 -80 4000 3500 3000
LTC2151-14: Shorted Input Histogram
50 45 40 IOVDD (mA) 35 30 25 20 15
LTC2151-14: IOVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS
LVDS CURRENT 3.5mA
2500 2000 1500 1000
LVDS CURRENT 1.75mA
-100 -120
500 0 20 40 60 80 FREQUENCY (MHz) 100
21521014 G32
0 8196
8200
8208 8204 OUTPUT CODE
8212
8216
215210 G33
0
50
100 150 200 SAMPLE RATE (Msps)
250
21521014 G34
LTC2151-14: IVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS
170 160 150 IVDD (mA) 140 130 120 110 120 100 SFDR (dBFS) 80 60 40 20
LTC2151-14: SFDR vs Input Level, fIN = 71MHz, 1.5V Range, 210Msps
dBFS
dBc
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0
50
100 150 200 SAMPLE RATE (Msps)
250
21521014 G35
0 -90 -80 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE (dBFS)
0
21521014 G36
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LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2151-14: SNR vs Input Level, fIN = 71MHz, 1.5V Range, 210Msps
20 70 60 50 SNR (dBFS) 40 30 20 10 0 -60 -50 -40 -30 -20 AMPLITUDE (dBFS) -10
21521014 G37
LTC2151-14: SFDR vs Input Level, -1dBFS, 1.5V Range, 210Msps
10 0 -10 INPUT LEVEL (dBc) SFDR (dBFS) 90 80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz)
21521014 G38
dBFS
dBc
-20 -30 -40 -50 -60 -70 0
LTC2151-14: SNR vs Input Level, -1dBFS, 1.5V Range, 210Msps
75 70 FS AMPLITUDE (-1dB) 65 SNR (dBFS) 60 55 50 45 40 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz)
21521014 G39
LTC2151-14: Frequency Response
-0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 100 1000 INPUT FREQUENCY (MHz)
21521014 G40
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LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2150-14: Integral Nonlinearity INL
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 4096 8192 12288 OUTPUT CODE 16384
21521014 G41
LTC2150-14: Differential Nonlinearity DNL
0.4
0 -20 AMPLITUDE (dBFS)
LTC2150-14: 32K Point FFT, fIN = 15MHz, -1dBFS, 170Msps
DNL ERROR (LSB)
INL ERROR (LSB)
0.2
-40 -60 -80
0
-0.2
-100 -0.4 0 4096 8192 12288 OUTPUT CODE 16384
21521014 G42
-120
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
21521014 G43
0 -20 AMPLITUDE (dBFS) -40 -60 -80
LTC2150-14: 32K Point FFT, fIN = 70MHz, -1dBFS, 170Msps
0 -20 AMPLITUDE (dBFS) 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80
21521014 G44
LTC2150-14: 32K Point FFT, fIN = 121MHz, -1dBFS, 170Msps
-40 -60 -80
-100 -120
-100 -120
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
21521014 G45
LTC2150-14: 32K Point FFT, fIN = 176MHz, -1dBFS, 170Msps
0 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -60 -80
LTC2150-14: 32K Point FFT, fIN = 225MHz, -1dBFS, 170Msps
0 -20 -40 -60 -80
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-100 -120
-100 -120
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
21521014 G46
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
21521014 G47
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LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL PERFORMANCE CHARACTERISTICS
0 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -60 -80
LTC2150-14: 32K Point FFT, fIN = 380MHz, -1dBFS, 170Msps
0 -20 -40 -60 -80
LTC2150-14: 32K Point FFT, fIN = 420MHz, -1dBFS, 170Msps
0 -20 AMPLITUDE (dBFS) 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80
21521014 G49
LTC2150-14: 32K Point FFT, fIN = 571MHz, -1dBFS, 170Msps
-40 -60 -80
-100 -120
-100 -120
-100 -120
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
21521014 G48
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
21521014 G50
0 -20 AMPLITUDE (dBFS) -40 -60 -80
LTC2150-14: 32K Point FFT, fIN = 907MHz, -1dBFS, 170Msps
LTC2150-14: 32K Point 2-Tone FFT, fIN = 70.5 and 69.5MHz, 170Msps
0 -20 AMPLITUDE (dBFS) -40 -60 -80 COUNT 4000 3500 3000 2500 2000 1500 1000
LTC2150-14: Shorted Input Histogram
-100 -120
-100 -120
500 0 10 20 30 40 50 60 70 INPUT FREQUENCY (MHz) 80
21521014 G52
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
21521014 G51
0 8196
8200
8208 8204 OUTPUT CODE
8212
8216
215210 G53
LTC2150-14: IOVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS
50 45 40 IOVDD (mA) 140 IVDD (mA) 250 35 30 25 20 15 0 50 100 150 200 SAMPLE RATE (Msps) LVDS CURRENT 1.75mA 130 120 110 LVDS CURRENT 3.5mA 160 150
LTC2150-14: IVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS
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0
50
21521014 G54
100 150 200 SAMPLE RATE (Msps)
250
21521014 G55
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LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2150-14: SFDR vs Input Level, fIN = 70MHz, 1.5V Range, 170Msps
120 100 SFDR (dBFS) 80 60 40 20 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE (dBFS) dBc dBFS 70 60 50 SNR (dBFS) 40 30 20 10 0 0 -60 -50 -40 -30 -20 AMPLITUDE (dBFS) -10
21521014 G57
LTC2150-14: SNR vs Input Level, fIN = 70MHz, 1.5V Range, 170Msps
dBFS
LTC2150-14: SFDR vs Input Frequency, -1dBFS, 1.5V Range, 170Msps
90 80 70 SFDR (dBFS) 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz)
21521014 G58
20 10 0 -10 INPUT LEVEL (dBc)
dBc
-20 -30 -40 -50 -60 -70 0
21521014 G56
LTC2150-14: SNR vs Input Frequency, -1dBFS, 1.5V Range, 170Msps
75 70 FS AMPLITUDE (-1dB) 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz)
21521014 G59
LTC2150-14: Frequency Response
-0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 100 1000 INPUT FREQUENCY (MHz)
65 SNR (dBFS) 60 55 50 45 40
21521014 G60
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LTC2152-14/ LTC2151-14/LTC2150-14 PIN FUNCTIONS
VDD (Pins 1, 2): 1.8V Analog Power Supply. Bypass to ground with 0.1F ceramic capacitor. Pins 1, 2 can share a bypass capacitor. GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC Power Ground. The exposed pad must be soldered to the PCB ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN- (Pin 5): Negative Differential Analog Input. SENSE (Pin 7): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a 0.75V input range. An external reference between 1.2V and 1.3V applied to SENSE selects an input range of 0.6 x VSENSE. VREF (Pin 8): Reference Voltage Output. Bypass to ground with a 2.2F ceramic capacitor. Nominally 1.25V. VCM (Pin 9): Common Mode Bias Output; nominally equal to 0.8V. VCM should be used to bias the common mode of the analog inputs. Bypass to ground with a 0.1F ceramic capacitor. ENC+ (Pin 11): Encode Input. Conversion starts on the rising edge. ENC- (Pin 12): Encode Complement Input. Conversion starts on the falling edge. OVDD (Pins 20, 30): 1.8V Output Driver Supply. Bypass to ground with a 0.1F ceramic capacitor. OGND (Pin 21): LVDS Driver Ground. SDO (Pin 36): In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an opendrain N-channel MOSFET output that requires an external 2k pull-up resistor from 1.8V to 3.3V. If readback from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. SDI (Pin 37): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In parallel programming mode (PAR/SER = VDD), SDI selects 3.5mA or 1.75mA LVDS output current (see Table 2). SCK (Pin 38): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In parallel programming mode (PAR/SER = VDD), SCK controls the sleep mode (see Table 2). CS (Pin 39): In serial programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/ SER = VDD), CS controls the clock duty cycle stabilizer (see Table 2). PAR/SER (Pin 40): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI and SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK and SDI become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal.
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LTC2152-14/ LTC2151-14/LTC2150-14 PIN FUNCTIONS
LVDS Outputs (DDR LVDS) The following pins are differential LVDS outputs. The output current level is programmable. There is an optional internal 100 termination resistor between the pins of each LVDS output pair. D0_1-/D0_1+ to D12_13-/D12_13+ (Pins 16/17, 18/19, 22/23, 24/25, 28/29, 31/32, 33/34): Double-Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13) appear when CLKOUT+ is high. CLKOUT -/CLKOUT+ (Pins 26/27): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. OF-/OF+ (Pins 14/15): Over/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred. This underflow is valid only when CLKOUT+ is low. In the second half clock cycle, the overflow is set to 0.
FUNCTIONAL BLOCK DIAGRAM
VDD OVDD D12_13 * * * D0_1
ANALOG INPUT
S/H
14-BIT PIPELINED ADC
CORRECTION LOGIC
OUTPUT DRIVERS
LVDS
VCM 0.1F
VCM BUFFER BUFFER CLOCK/DUTY CYCLE CONTROL
OGND
GND CLOCK VREF 2.2F 1.25V REFERENCE GND SENSE RANGE SELECT
SPI
CS SCK SDI SDO PAR/SER
GND
21521014 F01
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Figure 1. Functional Block Diagram
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LTC2152-14/ LTC2151-14/LTC2150-14 TIMING DIAGRAMS
Double-Data Rate Output Timing, All Outputs Are Differential LVDS
N tAP N+3 N+2 N+1 tH ENC- ENC+ tL
CLKOUT + CLKOUT - tC
D0_1- D0_1+ D12_13- D12_13+ OF - OF +
D0N-5 tD D12N-5
D1N-5
D0N-4
D1N-4
D0N-3
D1N-3
D13N-5
D12N-4
D13N-4
D12N-3
D13N-3
OFN-5
INVALID tSKEW
OFN-4
INVALID
OFN-3
INVALID
21521014 TD01
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LTC2152-14/ LTC2151-14/LTC2150-14 TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tS CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 XX D6 XX D5 XX D4 XX D3 XX D2 XX D1 XX D0 tDS tDH tSCK tH
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS SCK
SDI SDO
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
21521014 TD02
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LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
CONVERTER OPERATION The LTC2152-14/LTC2151-14/LTC2150-14 are 14-bit 250Msps/210Msps/170Msps A/D converters that are powered by a single 1.8V supply. The analog inputs must be driven differentially. The encode inputs should be driven differentially for optimal performance. The digital outputs are double-data rate LVDS. Additional features can be chosen by programming the mode control registers through a serial SPI port. ANALOG INPUT The analog inputs is a differential CMOS sample-andhold circuit (Figure 2). It must be driven differentially around a common mode voltage set by the VCM output pin, which is nominally 0.8V. The inputs should swing from VCM - 0.375V to VCM + 0.375V. There should be a 180 phase difference between the inputs. INPUT DRIVE CIRCUITS Input Filtering If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wide band noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application's input frequency. Transformer-Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with the common mode supplied through a pair of resistors via the VCM pin. At higher input frequencies a transmission line balun transformer (Figures 4 and 5) has better balance, resulting in lower A/D distortion.
10 0.1F 0.1F
LTC2152-14 VDD AIN+ 5 2pF VDD AIN- 5 2pF VDD RON 20 2pF RON 20 2pF
VCM LTC2152-14 AIN+ 10pF AIN-
21521014 F03
IN
T1 1:1 25 25
4.7
0.1F 4.7
T1: MACOM ETC1-1T
Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz
10
1.2V
VCM 0.1F LTC2152-14 AIN+
0.1F
10k ENC+ ENC www..com
-
IN
MABA 007159000000 T1 T1
T2 1:1 45
4.7
45
0.1F 4.7
100
0.1F
21521014 F02
AIN-
21521014 F04
Figure 2. Equivalent Input Circuit for Differential Input Clock
T1: MACOM ETC1-1-13
Figure 4. Recommended Front-End Circuit for Input Frequencies from 15MHz to 150MHz
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LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
VCM 0.1F IN MABA 007159000000 T1 10 4.7 45 0.1F 0.1F 45 4.7 AIN-
21521014 F05
Amplifier Circuits Figure 6 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier's output common mode voltage can be optimally set to minimize distortion. At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 3 and 5) should convert the signal to differential before driving the A/D. The A/D cannot be driven single-ended. Reference The LTC2152-14/LTC2151-14/LTC2150-14 has an internal 1.25V voltage reference. For a 1.5V input range with internal reference, connect SENSE to VDD. For a 1.5V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 7).
0.1F LTC2152-14 AIN+
100
T1: MACOM ETC1-1-13
Figure 5. Recommended Front-End Circuit for Input Frequencies from 150MHz Up to 900MHz
50
50
0.1F 3pF
VCM
Encode Input
LTC2152-14 AIN+ AIN-
0.1F INPUT
++
0.1F
4.7 3pF
--
4.7
The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals--do not route them next to digital traces on the circuit board. The encode inputs are internally biased to 1.2V through 10k equivalent resistance (Figure 8). If the common mode of the driver is within 1.1V to 1.5V, it is possible to drive
3pF
21521014 F06
Figure 6. Front-End Circuit Using a High Speed Differential Amplifier
LTC2152-14 1.25V 2.2F SCALER/ BUFFER ADC REFERENCE ENC+ 5 VREF
VDD
1.2V
10k
SENSE SENSE
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21521014 F07
ENC-
21521014 F08
Figure 7. Reference Circuit
Figure 8. Equivalent Encode Input Circuit
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LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
the encode inputs directly. Otherwise, a transformer or coupling capacitors are needed (Figures 9 and 10). The maximum (peak) voltage of the input signal should never exceed VDD +0.1V or go below -0.1V. Clock Duty Cycle Stabilizer For good performance the encode signal should have a 50% (5%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the encode signal changes frequency or is turned off, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. The duty cycle stabilizer is enabled via SPI Register A2 (see SPI Control Register) or by CS in parallel programming mode. For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. DIGITAL OUTPUTS The digital outputs are double-data rate LVDS signals. Two data bits are multiplexed and output on each differential output pair. There are seven LVDS output pairs (D0_1+/ D0_1- through D12_13-/D12_13+). Overflow (OF+/OF-) and the data output clock (CLKOUT+/CLKOUT-) each have an LVDS output pair. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage.
LTC2152-14
VDD
1.2V 0.1F 10k
T1
50 100
0.1F
50
21521014 F09
0.1F T1: MACOM ETC1-1-13
Figure 9. Sinusoidal Encode Drive
LTC2152-14 VDD
1.2V 0.1F
ENC+
10k
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PECL OR LVDS INPUT 100 0.1F ENC-
21521014 F10
Figure 10. PECL or LVDS Encode Drive
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LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
An external 100 differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND, which are isolated from the A/D core power and ground. Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3 (see Table 3). Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. Optional LVDS Driver Internal Termination In most cases, using just an external 100 termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100 termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Overflow Bit The overflow output bit (OF) outputs a logic high when the analog input is either overranged or underranged. The overflow bit has the same pipeline latency as the data bits. The OF is valid when CLKOUT+ is low. Phase Shifting the Output Clock To allow adequate set-up and hold time when latching the output data, the CLKOUT+ signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. Alternatively, the ADC can also phase shift the CLKOUT+/ CLKOUT- signals by serially programming mode control register A2. The output clock can be shifted by 0, 45, 90, or 135. To use the phase shifting feature, the clock duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and CLKOUT-, independently of the phase shift. The combination of these two features enables phase shifts of 45 up to 315 (Figure 11).
ENC+
D0-D13, OF PHASE SHIFT 0 45 90 135 180
MODE CONTROL BITS CLKINV 0 0 0 0 1 1 1 1 CLKPHASE1 0 0 1 1 0 0 1 1 CLKPHASE0 0 1 0 1 0 1 0 1
CLKOUT+
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225 270 315
21521014 F11
Figure 11. Phase Shifting CLKOUT
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LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
DATA FORMAT Table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. By default the output data format is offset binary. The 2's complement format can be selected by serially programming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ - AIN- >0.75 V +0.75V +0.749908V +0.0000915V +0.000000V -0.0000915V -0.0001831V -0.7499084V -0.75V < -0.75V (1.5V Range) OF 1 0 0 0 0 0 0 0 0 1 D13-D0 (OFFSET BINARY) 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 D13-D0 (2's COMPLEMENT) 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000
PC BOARD CLKOUT FPGA
D0 D0
21521014 F12
CLKOUT
CLKOUT
OF D13
OF
D13/D0
D12 RANDOMIZER ON D1
* * *
D12/D0
D1/D0
Figure 12. Functional Equivalent of Digital Output Randomizer
Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off-chip, these unwanted tones can be randomized, which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied--an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled by serially programming mode control register A4.
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OF D13/D0 LTC215X-14 D12/D0 D13
D1/D0
* * *
D12
D1
D0
D0
21521014 F13
Figure 13. Unrandomizing for Randomized Digital Output Signal
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LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
Alternate Bit Polarity Another feature that may reduce digital feedback on the circuit board is the alternate bit polarity mode. When this mode is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11, D13) are inverted before the output buffers. The even bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not affected. This can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate bit polarity mode is independent of the digital output randomizer--either both or neither function can be on at the same time. The alternate bit polarity mode is enabled by serially programming mode control register A4. Digital Output Test Patterns To allow in-circuit testing of the digital interface to the A/D, there are several test modes (activate by setting DTESTON) that force the A/D data outputs (OF D13 to , D0) to known values: All 1s: All outputs are 1 All 0s: All outputs are 0 Alternating: Outputs change from all 1s to all 0s on alternating samples Checkerboard: Outputs change from 101010101010101 to 010101010101010 on alternating samples. The digital output test patterns are enabled by serially programming mode control register A4. When enabled, the test patterns override all other formatting modes: 2's complement, randomizer, alternate-bit polarity. Output Disable The digital outputs may be disabled by serially programming mode control www..com register A3. All digital outputs, including OF and CLKOUT, are disabled. The high impedance disabled state is intended for long periods of inactivity, it is not designed for multiplexing the data bus between multiple converters. Power-Down Modes The A/D may be placed in a power-down mode to conserve power. In sleep mode, the entire A/D converter is powered down, resulting in < 2mW power consumption. If the encode input signal is not disabled, the power consumption will be higher (up to 2mW at 250Msps). Sleep mode is enabled by mode control register A1 (serial programming mode), or by SCK (parallel programming mode). In serial programming mode it is also possible to disable channel B while leaving channel A in normal operation. The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF . For the suggested values in Figure 1, the A/D will stabilize after 0.1ms + 2500 * tp where tp is the period of the sampling clock. Nap Mode In nap mode the A/D core is powered down while the internal reference circuits stay active, allowing faster wakeup. Recovering from nap mode requires at least 100 clock cycles. Wake-up time from nap mode is guaranteed only if the clock is kept running, otherwise power-down, wake-up time conditions apply. Nap mode is enabled by power-down register A1 in the serial programming mode. DEVICE PROGRAMMING MODES The operating modes of the LTC215X-14 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK and SDI pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
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LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
CMOS logic. Table 2 shows the modes set by CS, SCK and SDI.
Table 2. Parallel Programming Mode Control Bits)
PIN CS DESCRIPTION Clock Duty Cycle Stabilizer Control Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On SCK Power-Down Control Bit 0 = Normal Operation 1 = Sleep Mode (entire ADC is powered down) SDI LVDS Current Selection Bit 0 = 3.5mA LVDS Current Mode 1 = 1.75mA LVDS Current Mode
Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset it is necessary to write 1 in register A0 (Bit D7). After the reset is complete, Bit D7 is automatically set back to zero. GROUNDING AND BYPASSING The LTC215X-14 requires a printed circuit board with a clean unbroken ground plane in the first layer beneath the ADC. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM and VREF pins. Bypass capacitors must be located as close to the pins as possible. Size 0402 ceramic capacitors are recommended. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The analog inputs, encode signals and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC215X-14 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias.
Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first sixteen rising edges of SCK. Any SCK rising edges after the first sixteen are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the Timing Diagrams). During a readback command the register is not updated and data on SDI is ignored. The SDO pin is an open-drain output that pulls to ground with a 200 impedance. If register data is read back through SDO, an www..comexternal 2k pull-up resistor is required. If serial data is only written and readback is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers.
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LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). An "X" indicates an unused bit.
REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 RESET Bit 7 RESET D6 X D5 X Software Reset Bit D4 X D3 X D2 X D1 X D0 X
0 = Not Used 1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete. Bits 6-0 Unused Unused Bit Read Back as 0 REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h) D7 X Bit 3 D6 X D5 X D4 X D3 SLEEP D2 NAP D1 0 D0 0
SLEEP 0 = Normal Operation 1 = Power Down Entire ADC NAP 0 = Normal Mode 1 = Low Power Mode
Bit 2
Bit 1-0
Must be set to 0 at all times
Unused Bit Read Back as 0 REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 X Bit 3 D6 X D5 X D4 X D3 CLKINV D2 CLKPHASE1 D1 CLKPHASE0 D0 DCS
CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams) 1 = Inverted CLKOUT Polarity CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits 00 = No CLKOUT Delay (as shown in the Timing Diagrams) 01 = CLKOUT+/CLKOUT- delayed by 45 (Clock Period * 1/8) 10 = CLKOUT+/CLKOUT- delayed by 90 (Clock Period * 1/4) 11 = CLKOUT+/CLKOUT- delayed by 135 (Clock Period * 3/8) Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on. DCS Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On
Bits 2-1
Bit 0
Unused Bit Read Back as 0
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26
LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h) D7 X Bits 4-2 D6 X D5 X D4 ILVDS2 D3 ILVDS1 D2 ILVDS0 D1 TERMON D0 OUTOFF
ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS output driver current is 2x the current set by ILVDS2:ILVDS0 OUTOFF Digital Output Mode Control Bits 0 = LVDS DDR 1 = LVDS Tristate (High Impedance)
Bit 1
Bit 0
Unused Bit Read Back as 0 REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 OUTTEST2 Bits 7-5 D6 OUTTEST1 D5 OUTTEST0 D4 ABP D3 X D2 DTESTON D1 RAND D0 TWOSCOMP
OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = All Digital Outputs = 0 001 = All Digital Outputs = 1 010 = Alternating Output Pattern. OF D13-D0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111 , 100 = Checkerboard Output Pattern. OF D13-D0 alternate between 010 1010 1010 1010 and 101 0101 0101 0101 , ABP Alternate Bit Polarity Mode Control Bit 0 = Alternate Bit Polarity Mode Off 1 = Alternate Bit Polarity Mode On Must be set to 0 at all times DTESTON Enable digital patterns (Bits 7-5) 0 = Normal Mode 1 = Enable the Digital Output Test Patterns RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On TWOSCOMP Two's Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two's Complement Data Format
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Unused Bit Read Back as 0
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27
LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
215210 F14
Silkscreen Top
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Inner Layer 1 GND
215210 F15
Inner Layer 2
215210 F16
Inner Layer 3
215210 F17
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28
LTC2152-14/ LTC2151-14/LTC2150-14 APPLICATIONS INFORMATION
215210 F18
215210 F19
215210 F20
Inner Layer 4
Inner Layer 5
Bottom Layer 6
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29
LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL APPLICATIONS
VDD OVDD
REGULATED 1.8V C10 1F
L4 BEAD C11 47F 1210
+
L5 BEAD C12 0.1F C34 0.1F C35 0.1F
VDD 0.2F TP3 SENSE R14 10 R16 100 C13 2.2F R9, 1k VDD VDD GND AINA+ AINA- GND SENSE VREF VCM GND GND C21 0.1F PAR/SER CS SCK SDI SDO GND D12_13+ D12_13- D10_11+ D10_11- 0.1F
40 39 38 37 36 35 34 33 32 31
D12_13+ D12_13- D10_11+ D10_11-
SDO SDI SCK CS PAR/SER
AINA+
AINA-
R19 10
SENSE C16 2.2F 10
1 2 3 4 5 6 7 8 9 10 41
LTC2152
30 29 28 27 26 25 24 23 22 21
OVDD D8_9+ D8_9- CLKOUT+ CLKOUT - D6_7+ D6_7- D4_5+ D4_5- OGND
OVDD D8_9+ D8_9- CLKOUT+ CLKOUT - D6_7+ D6_7 - D4_5+ D4_5-
CLK+ CLK- GND OF - OF + D0_1- D0_1+ D2_3- D2_3+ OVDD
11 12 13 14 15 16 17 18 19 20 0.1F OF - OF + D0_1- D0_1+ D2_3- D2_3+ OVDD 0.1F CLK-
21521014 TA02
0.1F CLK
+
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30
LTC2152-14/ LTC2151-14/LTC2150-14 PACKAGE DESCRIPTION
(Reference LTC DWG # 05-08-1728 Rev O)
UJ Package 40-Lead Plastic QFN (6mm x 6mm)
0.70 0.05
6.50 0.05 4.42 0.05 5.10 0.05 4.50 0.05 (4 SIDES)
4.42 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 0.10 (4 SIDES)
0.75 0.05 R = 0.10 TYP
R = 0.115 TYP
39 40 0.40 0.10 1 PIN 1 NOTCH R = 0.45 OR 0.35 45 CHAMFER 2
PIN 1 TOP MARK (SEE NOTE 6)
4.50 REF (4-SIDES)
4.42 0.10
4.42 0.10
(UJ40) QFN REV O 0406
0.200 REF
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
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0.00 - 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2152-14/ LTC2151-14/LTC2150-14 TYPICAL APPLICATION
LTC2152-14 32K Point FFT, fIN = 15MHz, -1dBFS, 250Msps
VDD OVDD
-20 AMPLITUDE (dBFS) 0
ANALOG INPUT
S/H
14-BIT PIPELINED ADC
CORRECTION LOGIC
OUTPUT DRIVERS
D12_13 * * * D0_1
DDR LVDS
-40 -60 -80
CLOCK
CLOCK/DUTY CYCLE CONTROL
21521014 TA03a
OGND
-100 -120
0
20
40 60 80 100 FREQUENCY (MHz)
120
21521014 TA03b
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32 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0311 * PRINTED IN USA
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2011

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